Сделай шаг к ПЛИС

module test01(clk, out);

input wire clk;

output reg [7:0] out;

initial begin
  out = 0;
end

always @(posedge clk) begin
  out <= out + 1;
end

endmodule

module test01(data, SEG);

input wire[3:0] data;
output wire[7:0] SEG;

reg [6:0] SEG_buf;
always @ (data)
  begin
    case(data)
      4'h0: SEG_buf <= 7'b0111111;
      4'h1: SEG_buf <= 7'b0000110;
      4'h2: SEG_buf <= 7'b1011011;
      4'h3: SEG_buf <= 7'b1001111;
      4'h4: SEG_buf <= 7'b1100110;
      4'h5: SEG_buf <= 7'b1101101;
      4'h6: SEG_buf <= 7'b1111101;
      4'h7: SEG_buf <= 7'b0000111;
      4'h8: SEG_buf <= 7'b1111111;
      4'h9: SEG_buf <= 7'b1101111;
      4'hA: SEG_buf <= 7'b1110111;
      4'hB: SEG_buf <= 7'b1111100;
      4'hC: SEG_buf <= 7'b0111001;
      4'hD: SEG_buf <= 7'b1011110;
      4'hE: SEG_buf <= 7'b1111001;
      4'hF: SEG_buf <= 7'b1110001;
      default: SEG_buf <= 7'b0111111;
    endcase
  end 
  
  assign SEG = {1'b0,SEG_buf};

endmodule

module stepdir(input STEP, input DIR,output reg [3:0] OUT);
reg [3:0] state;

initial
begin
  state=0;
end

always@(posedge STEP)begin
	if (DIR==1) begin
	  state=state+1'b1;
	end else	if (DIR==0) begin
	  state=state-1'b1;
	end

	case (state)
	  0: OUT=4'b1000;
	  1: OUT=4'b1100;
	  2: OUT=4'b0100;
	  3: OUT=4'b0110;
	  4: OUT=4'b0010;
	  5: OUT=4'b0011;
	  6: OUT=4'b0001;
	  7: OUT=4'b1001;
   endcase
end
		  
endmodule

module test01(clk, SCK, MOSI, MISO, SSEL, LED, PWM_out);
input clk;

input SCK, SSEL, MOSI;
output MISO;
output LED;
output PWM_out;

// sync SCK to the FPGA clock using a 3-bits shift register
reg [2:0] SCKr;  always @(posedge clk) SCKr <= {SCKr[1:0], SCK};
wire SCK_risingedge = (SCKr[2:1]==2'b01);  // now we can detect SCK rising edges
wire SCK_fallingedge = (SCKr[2:1]==2'b10);  // and falling edges

// same thing for SSEL
reg [2:0] SSELr;  always @(posedge clk) SSELr <= {SSELr[1:0], SSEL};
wire SSEL_active = ~SSELr[1];  // SSEL is active low
wire SSEL_startmessage = (SSELr[2:1]==2'b10);  // message starts at falling edge
wire SSEL_endmessage = (SSELr[2:1]==2'b01);  // message stops at rising edge

// and for MOSI
reg [1:0] MOSIr;  always @(posedge clk) MOSIr <= {MOSIr[0], MOSI};
wire MOSI_data = MOSIr[1];

// we handle SPI in 8-bits format, so we need a 3 bits counter to count the bits as they come in
reg [2:0] bitcnt;

reg byte_received;  // high when a byte has been received
reg [7:0] byte_data_received;

reg [7:0] pwm_counter;

initial
  pwm_counter = 0;
  
always @(posedge clk)
  pwm_counter <= pwm_counter + 1;
  
assign PWM_out = (byte_data_received>pwm_counter);  // comparator

always @(posedge clk)
begin
  if(~SSEL_active)
    bitcnt <= 3'b000;
  else
  if(SCK_risingedge)
  begin
    bitcnt <= bitcnt + 3'b001;

    // implement a shift-left register (since we receive the data MSB first)
    byte_data_received <= {byte_data_received[6:0], MOSI_data};
  end
end

always @(posedge clk) byte_received <= SSEL_active && SCK_risingedge && (bitcnt==3'b111);

// we use the LSB of the data received to control an LED
reg LED;
always @(posedge clk) if(byte_received) LED <= byte_data_received[0];

endmodule